A Design of a Dual Delay Line DLL with Wide Input Duty Cycle Range

This article describes a dual-controller dual-delay line delay lock loop (DC-DL DLL). The proposed DLL adopted dual structure, each was composed of coarse adjustment and fine unit, the lines had corresponding control units to reduce mismatch between lines, it avoided complicated design duty cycle correction (DCC) circuit. A frequency divider added divide input clock achieve wider adjustment. Additionally, simple synthesis circuit synthesize required clock. used 25 nm process with voltage 1.2 V. simulation results showed that at working 1.6 GHz, peak-to-peak jitter DC-DL after locking approximately 17.61 ps, maximum output error about 1.3%, ranged from 20% 80%, power consumption 10.06 mW.